1. Field of the Invention
The present invention relates to a reduction in a sealing thickness of a semiconductor device constructed by stacking semiconductor chips.
2. Description of the Invention
In the prior art, for a flash memory card such as the compact flash card, etc. used as the storing medium for a camera, a cam corder, etc., the TSOP (Thin Small Outline Package) which allows a relatively large space in the card and having a standard type package thickness dimension of 1.2 mm, at maximum, is employed. Recently, a smaller flash card was developed, reducing the space in the card, so there is the request that the thickness of the package should be reduced to an about half of the standard TSOP. Also, there is a strong request to make the capacity larger. To avoid attaining a larger capacity in a single semiconductor chip, a semiconductor device called an MCP (Multi Chip Package) in which two semiconductor chips are sealed with a sealant was developed.
FIG. 11 is a sectional view of the MCP in the prior art, that is disclosed in Patent Application Publication (KOHYO) Hei 10-506226, for example, and is constructed by sticking two semiconductor chips onto two surfaces of a die pad of a sheet of lead frame to mount such two semiconductor chips thereon.
The semiconductor chip 3 is jointed to the first surface (that is shown on the upper side of the die pad 1 in FIG. 11) of the die pad 1 via the jointing material 2. The semiconductor chip 5 is jointed to the second surface (that is shown on the lower side of the die pad 1 in FIG. 11) of the die pad 1 via the jointing material 4. Thus, in FIG. 11, the stacked semiconductor chip (the semiconductor chip having both active surfaces) is constructed such that the active surface 3a and the active surface 5a put the die pad 1 and the jointing materials 2, 4 between the top surface and the bottom surface respectively.
One ends of the gold wires 6 are connected to pads (not shown) provided to the active surfaces 3a and 5a via the ball bonding 6c. The other ends of the gold wires 6 are connected to one surfaces 7a of the inner leads 7 and the other surfaces 7b of the inner leads 7 to shift the positions of the stitch bonding 6d. The wire bonding method in which the ball bonding 6c is applied to the pads provided on the semiconductor chips 3, 5 and the stitch bonding 6d is applied to the inner leads 7 is normally carried out in the prior art, and is called the forward wire bonding method.
In FIG. 11, the highest portions 6a, 6b of the gold wires 6 are covered with the sealing resin 8 by the dimension E to seal and protect. The sum E+A+B+A+E of the height dimension A of the highest portions 6b of the gold wires extended upward from the active surface 3a shown in FIG. 11, the thickness B of the stacked semiconductor chip (sum of the semiconductor chips 3, 5, the jointing materials 2, 4 and the die pad 1), the height dimension A of the highest portions 6b of the gold wires extended downward from the active surface 5a, and the dimension E to cover the highest portions of the gold wires 6 gives the total thickness dimension of the MCP.
In the semiconductor device described above in the prior art, there is the drawback that, since the thickness B of the stacked semiconductor chip is given by the sum of the semiconductor chips 3, 5, the jointing materials 2, 4 and the die pad 1, the thickness of the die pad 1 increases the thickness of the both-surface semiconductor chip.
Also, in the forward wire bonding method, there is the drawback that, since the sum D=A+C of the dimension A between the position of the ball bonding 6c and the highest portions 6a or 6b of the gold wires and the dimension C from the position of the ball bonding 6c to the highest portions 6a of the gold wires gives the height dimension from the stitch bonding position to the highest portions of the gold wires, such dimension A overlaps with the above height dimension and thus the gold wires are extended longer by such dimension.
In addition, if the forward wire bonding is applied to the center-pad-arrangement semiconductor chip in which the pads are arranged in the center of the active surface of the semiconductor chip, there is the drawback that, since the gold wires come into contact with the outer periphery of the stacked semiconductor chip, it is impossible to apply the wire bonding to such semiconductor chip.
If the thickness of the semiconductor device must be reduced to 0.5 mm by the structure in the prior art, there is the problem that, unless the thickness of the stacked semiconductor chip can be reduced to less than 0.025 mm with regard to the thickness of two sheets of the jointing material 2xc3x970.025 mm, the metal wire loop height A=0.15 mm to 0.18 mm, and the lead frame plate thickness 0.125 mm, the metal wires 6 are exposed from the outer surface of the sealing resin 8.
If the thickness of the semiconductor chip is reduced to less than 0.1 mm, various problems to be newly overcome have arisen, e.g., the problem that the polishing of the wafer becomes difficult, the problem that the failure occurs when the wafer is carried after the polishing, the problem that the failure occurs when the wafer is divided into individual chips, the problem that the failure occurs when divided semiconductor chips are assembled, etc. Thus, there is the problem that the mass production equipment in the prior art cannot deal with such problems.
Furthermore, if the thickness of the semiconductor device is thin such as 0.5 mm, the height of the external leads is lowered such as 0.25 mm, which is an almost half of the thickness 0.5 mm of the semiconductor device, when the external leads 7 whose plate thickness is 0.125 mm are extracted from the central side surfaces of the semiconductor device, as set forth in Patent Application Publication (KOHYO) Hei 10-506226. Therefore, there is caused the problem that, since it is impossible to sufficiently absorb the thermal strain that is caused by the change in the ambient temperature after the semiconductor device is packaged onto the packaging substrate, there liability margin of the solder jointed portion is reduced.
Therefore, the present invention intends to provide a semiconductor device having a thickness that is a half of the normalized thickness of the semiconductor device in the prior art, by overcoming the above-mentioned drawbacks in the prior art.
It is an object of the present invention to provide a semiconductor device that is able to shorten a useless and redundant routing of metal wires and reduce a sealing thickness, by constructing stacked semiconductor chips, that are stacked like a stairs, and a loop height of the metal wire not to increase a thickness of the semiconductor device.
To achieve the above object, according to the invention, there is provided a semiconductor device in which a stacked semiconductor chip formed of semiconductor chips that have a principal surface on peripheries of which the pads are arranged and a back surface which opposes to the principal surface respectively, by fixing the back surface of the other semiconductor chip positioned on the upper side onto the principal surface of one semiconductor chip positioned on the lower side by a jointing material not to cover pads like a stairs, and a lead frame is employed in which inner leads and outer leads are continuously formed and in which a die pad, from which die pad suspending leads having a die pad sink are continuously formed, is formed. The back surface of the stacked semiconductor chip is fixed to one surface of the die pad by the jointing material. The pads on the stacked semiconductor chip and corresponding inner leads are connected via the metal wires by a backward wire bonding, and then five major surfaces of the inner leads, the stacked semiconductor chip, the metal wires, the jointing materials, and the die pad are covered with the sealing material to expose the back surface of the die pad from an outer surface of the sealing resin.
Also, according to the invention, the stacked semiconductor chip is formed by stacking the upper semiconductor chip after the upper semiconductor chip is turned by 180 degree in a same plane and is shifted like a stairs, and then fixing it not to cover the pads provided on the lower semiconductor chip.
In addition, the stacked semiconductor chip is formed of two different semiconductor chips such that the pads provided on the principal surface of the lower semiconductor chip are exposed from an outer peripheral area of the upper semiconductor chip.
Further, the back surface of the stacked semiconductor chip is fixed to a thinned portion of the die pad by the jointing material.
Furthermore, top end portions of the inner leads to which a level difference is provided and the corresponding pads provided on the level difference portions of the stacked semiconductor chip are connected by the backward wire bonding.
One ends of the metal wires are connected to one surfaces of the inner leads, that are positioned within a stacked thickness range of the stacked semiconductor chip, by a ball bonding, and other ends of the metal wires are connected to the pads, that are provided to the principal surface of the upper semiconductor chip of the stacked semiconductor chip, by a stitch bonding.